----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:38:56 09/15/2012 
-- Design Name: 
-- Module Name:    SignExtend - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library WORK;
use WORK.MIPS_CONSTANT_PKG.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SignExtend is
	port(
		signExtendIn : in std_logic_vector(15 downto 0);
		signExtendOut : out std_logic_vector(31 downto 0)
	);
end SignExtend;

architecture Behavioral of SignExtend is
begin
	SignExtendProc : process(signExtendIn )
	begin
		if signExtendIn (15) = '0' then
			signExtendOut <= ZERO16b & signExtendIn ;
		else 
			signExtendOut <= ONE16b & signExtendIn ;
		end if;
	end process;
end Behavioral;